Yap, Roderick Y. (1993) Programmable cyclic redundancy check encoder/decoder with VLSI implementation. Masters thesis, De La Salle University - Dasmariñas.
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ABSTRACT see Upload (MT ENGRNG 43 1993)
Item Type: | Thesis (Masters) |
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Additional Information: | MT ENGRNG 43 1993 |
Subjects: | T Technology > T Technology (General) |
Users: | College of Engineering, Architecture and Technology > Technology |
Depositing User: | Ivyjoy Viray |
Date Deposited: | 29 Jun 2016 08:27 |
Last Modified: | 21 Apr 2022 15:01 |
URI: | http://thesis.dlsud.edu.ph/id/eprint/3943 |
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