Reduction integrated circuits (IC) test time through statistical set-up verifier (SSUV).

Dimal, Reynilan L. (2020) Reduction integrated circuits (IC) test time through statistical set-up verifier (SSUV). Masters thesis, De La Salle University-Dasmariñas.

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Abstract

ABSTRACT See Upload (MT ENGRNG 067 2020) ACCESS TO THESIS WITH RESTRCITION : DLSU-D Community / DLSU-D Administrators and Faculty only.

Item Type: Thesis (Masters)
Additional Information: MT ENGRNG 067 2020
Subjects: T Technology > T Technology (General)
T Technology > TA Engineering (General). Civil engineering (General)
T Technology > TK Electrical engineering. Electronics Nuclear engineering
Users: College of Engineering, Architecture and Technology > Engineering
Depositing User: Users 1371 not found.
Date Deposited: 20 Jan 2021 00:32
Last Modified: 17 Jul 2024 02:59
URI: https://thesis.dlsud.edu.ph/id/eprint/7101

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