Dimal, Reynilan L. (2020) Reduction integrated circuits (IC) test time through statistical set-up verifier (SSUV). Masters thesis, De La Salle University-Dasmariñas.

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Abstract

ABSTRACT See Upload (MT ENGRNG 067 2020)

Item Type:	Thesis (Masters)
Additional Information:	MT ENGRNG 067 2020
Subjects:	T Technology > T Technology (General) T Technology > TA Engineering (General). Civil engineering (General) T Technology > TK Electrical engineering. Electronics Nuclear engineering
Users:	College of Engineering, Architecture and Technology > Engineering
Depositing User:	Users 1371 not found.
Date Deposited:	20 Jan 2021 00:32
Last Modified:	03 Mar 2022 05:15
URI:	https://thesis.dlsud.edu.ph/id/eprint/7101

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